As seen in FIG. 1, the design cycle for a VLSI device involves a series of steps such as that indicated by step A, B, C,. . . J. The time factor in this design cycle may involve periods of 8 to 10 weeks to reach the point of step J which is the system debug operation.
During the "debug" phase of any logic system development, it is always necessary to make hardware changes as various logic "bugs" are found. That is to say, when the originally designed system does not operate as required or desired, it is then necessary to do something to make the system perform as later-realized requirements necessitate.
When the hardware of a system is implemented in standard SSI (Small Scale Integration) and in MSI (Medium Scale Integration) logic chips on logic boards, the necessary hardware changes can often be done quickly by the "cutting" of the board etch and the adding on of patch wires.
As the generation of custom VLSI gate array chips becomes more and more a part of system logic design, then the hardware changes may be difficult or impossible to effectuate. If the changes are "external" to the VLSI chip, then the formerly known techniques of "cutting and adding" can then be used, but, if the problem is found to reside "internally" to the VLSI device, then the physical changes required cannot be done in a short time frame since then, the VLSI design must be "recycled" through the VLSI design cycle shown in FIG. 1 with steps A, B, C,. . . H, I, J having to be reformulated.
This cycle may take as long as another 8 to 10 week period, as previously mentioned, in order to get a new set of prototype chips so that the system debug operation at step J of FIG. 1, can then continue. These types of delays are normally not acceptable in a design schedule for a system.
The simulation phase at step D of FIG. 1 of the design cycle is intended to help eliminate logic errors in the VLSI chip device. A careful, extensive, and intelligent approach to this phase can reduce the possibility of errors. However, experience has shown that rarely is it possible to simulate all the possible and necessary system functions and architecture that will be required for the final operating system.
The present disclosure provides a method of architectural arrangement to overcome the problems encountered in preliminary design when it is not possible for the logic designer to anticipate all the future problem areas or even to anticipate unknown requirements which may show up later. Thus a flexible and alterable design is the lifesaving solution or, that is to say, the design-saving solution during the course of the custom VLSI development cycle.